1. Field of the Invention
The present invention relates to a method of driving an image display device to which a digital video signal is input and to an image display device for which the driving method is used. Further, the present invention relates to an electronic device using the image display device.
2. Description of the Related Art
In recent years, research and development of a thin film transistor (TFT) using a polycrystalline silicon film as an active layer has been actively made. The mobility in the TFT using a polycrystalline silicon film is two orders of magnitude higher than that in a TFT using an amorphous silicon film. Thus, even if the gate width of the TFT is reduced for microfabrication, a current value enough to operate a circuit can be secured. Therefore, a system-on-panel can be realized in which a pixel portion and a driver circuit thereof in an active matrix flat panel display are integrally formed on the same substrate.
If the system-on-panel is realized, a cost reduction due to reductions in the number of assembly steps and test steps for a display is enabled and miniaturization and high definition of a flat panel display are also enabled.
Incidentally, driver circuits of an image display device include a driver circuit using an analog video signal and a driver circuit using a digital video signal. In the case of the driver circuit using a digital video signal, a digital system broadcast wave can be input to the driver circuit as it is without being converted into an analog signal. The driver circuit can be adaptable to a recent digital broadcast, and thus has a promise.
FIG. 20 shows a general structure of an active matrix liquid crystal display device as a kind of an active matrix image display device driven using a digital video signal. As shown in FIG. 20, the liquid crystal display device comprises a signal line driver circuit 9001, a scanning line driver circuit 9002, a pixel portion 9003, signal lines 9004, scanning lines 9005, pixel TFTs 9006, liquid crystal cells 9007, and the like. Each of the liquid crystal cells 9007 includes a pixel electrode, a counter electrode, and liquid crystal provided between the pixel electrode and the counter electrode.
FIG. 21 shows a detailed structure of the signal line driver circuit 9001. FIG. 22 is a timing chart in the signal line driver circuit shown in FIG. 21. Here, an example of an image display device having k (horizontal)×l (vertical) pixels will be described. In order to make easy description, the case where a digital video signal is 3 bits will be indicated as an example. However, the number of bits in an actual image display device is not limited to 3. Also, it is indicated using a concrete value of k=640 in FIGS. 21 and 22.
A general signal line driver circuit includes mainly a shift register 9100, first and second memory circuit groups 9101 and 9102, and a D/A converter circuit group 9103. The shift register 9100 has a plurality of delay type flip flops (DFF). Also, the first memory circuit group 9101 and the second memory circuit group 9102 have a plurality of first memory circuits and a plurality of second memory circuits, respectively. Note that in FIG. 21, a first latch (LAT1) is used as the first memory circuit and a second latch (LAT2) is used as the second memory circuit. The D/A converter circuit group 9103 includes a plurality of D/A converter circuits (DAC).
In the shift register 9100, an output signal pulse is sequentially shifted in accordance with an input clock signal for the signal line driver circuit (S-CLK) and a start pulse for the signal line driver circuit (S-SP). The first memory circuit group 9101 stores digital video signals in succession in synchronization with output signals of the shift register 9100. The second memory circuit group 9102 stores outputs of the first memory circuit group 9101 in synchronization with latch pulses. The D/A converter circuit group 9103 converts output signals of the second memory circuit group 9102 into analog signals.
Hereinafter, more detailed structure and operation of the above signal line driver circuit will be described. The number of stages in DFFs of the above-mentioned shift register 9100 (corresponding to the number of DFFs shown in FIG. 21) becomes k+1 because the number of pixels in a horizontal direction is “k”. As shown in FIG. 22, each of control signals (SR-001 to SR-640 in FIG. 21) as the output signals of the shift register has a pulse shifted by one cycle of S-CLK. The control signals (SR-001 to SR-640) are directly input to the first latches (LAT1) of the first memory circuit group 9101 or are input thereto through buffers.
The first latches (LAT1) store input digital video signals of 3 bits (D0 to D2) in synchronization with the control signals. When pulses of the control signals output from the shift register 9100 are shifted by the same number of items as the number of pixels “k” of one line digital video signals corresponding to pixels of one line are stored in the first latches (LAT1). Thus, 3 (the number of bits in a digital video signal)×k (the number of pixels in a horizontal direction) first latches (LAT1) are required.
Next during a flyback period, the second latches (LAT2) of the second memory circuit group 9102 are operated in response to an input latch pulse (LP) and the digital video signals (L1-001 to L1-640 in FIGS. 21 and 22) which have been stored in the first latches (LAT1) are stored in the second latches (LAT2). Thus, 3×k second latches (LAT2) are similarly required. Note that reference symbols L1-001 to L1-640 are indicated in FIG. 21 by assigning a number to each corresponding pixel independent of the number of bits.
When the flyback period is elapsed and a next horizontal scanning period is started, the shift register 9100 again initiates to operate and outputs control signals. Thus, inputs of digital video signals (D0 to D2) to the first latches (LAT1) are started. On the other hand, the digital video signals (L2-001 to L2-640) which have been stored in the second latches (LAT2) are converted into analog signals by the D/A converter circuits (DAC) of the D/A converter circuit group 9103 and input as analog video signals to respective source signal lines (S1 to S640). When pixel TFTs of the respective pixels are turned on, the analog video signals are written into pixel electrodes of the liquid crystal cells.
By the above operation, the image display device performs image display.
The digital system driver circuit which performs the above operation has a defect that an occupying area is very larger than that in an analog system driver circuit. The digital system has a merit that a signal can be indicated by using only binary states “Hi” and “Lo”. However, an enormous amount of data is required and the number of circuit elements is increased for processing the data. Thus, an increase in an occupying area of the driver circuit on a substrate cannot be suppressed and this becomes a large hindrance to miniaturization of an image display device.
Also, recently, an increase in the number of pixels and high definition of a pixel are aimed at with a significant increase in the amount of information to be treated. However, it is expected that the number of circuit elements included in a driver circuit is also increased with the increase in the number of pixels and an area of the driver circuit is increased.
Here, an example of a display resolution generally used in a computer is indicated below using the number of pixels and standard names.
Number of PixelsStandard Name640 × 480VGA800 × 600SVGA1024 × 768 XGA1280 × 1024SXGA1600 × 1200UXGA
For example, it is assumed that the number of bits is 8 in the SXGA standard. In this case, when 1280 signal lines are provided in the above-mentioned conventional driver circuit, 10240 (8×1280) first memory circuits and 10240 (8×1280) second memory circuits are required. Also, a high definition television receiver such as a high definition TV (HDTV) becomes widely available and a high definition image is required in not only a computer world but also an audio-visual field. A ground digital broadcast begins in America. Also, Japan moves into the age of a digital broadcast. In a digital broadcast, a standard that the number of pixels is 1920 ×1080 is strong and prompt miniaturization of the driver circuit is desired.
However, as described above, the occupying area of the signal line driver circuit is large and this hinders the miniaturization of the image display device.